Novel logic goals to beat CMOS, on 10 yr older fabs


It could “allow chip designers to supply ICs in older 180nm, and even one micron, geometry fabs with the equal efficiency of CMOS units made in state-of-the-art vegetation”, in line with the corporate. “For instance, a fab geared up with 180nm photolithographic steppers might now produce units with the scale, pace and efficiency of 35nm CMOS.”

Behind its claims are the corporate’s novel tunnelling transistors (now branded Zpolar), a producing course of (dubbed Bizen) which makes the transistors on previous CMOS fabs, and a few-transistor low-data-voltage non-complementary logic system utilizing the transistors (branded ZTL).

Space beneficial properties over CMOS, in line with the corporate, are due excessive transistor conductivity resulting in small transistors, and fewer transistors – most ZTL logic gates have just one – which reduces the necessity for space-consuming conductors inside a logic cell. Learn additional down for extra technical element.

Characterisation has allowed SFN to announce 4 IC design packages, branded ITMs. The corporate describes them like this:

  • ITM180, which may ship chips with the efficiency of 180nm CMOS utilizing one micron gear
  • ITM35, which permits 35nm CMOS-equivalent ICs to be made in 180nm course of node fabs
  • ITM5 which permits 5nm CMOS efficiency from 28nm steppers
  • ITMSubnm which signifies that present state-of-the-art 3nm fabs will be capable to ship sub-nm, Angstrom-level capabilities

“VHDL is taken into the chosen ITM – dependant on efficiency necessities – from chip designers,” it mentioned. “The ITM, which accommodates the fully-characterised LIB [device libraries] and PDK [process development kit], provides each the POR [process of reference] and GDSii info to the foundries to make the ZTL chip.”

Can we have now a sensible instance? 

SFN has produced a theoretical comparability utilizing a 0.35μm CMOS Pentium 2, and an equal ZTL system optimised in three other ways:

CMOS 0.35μm Pentium 2 (Klamath) CMOS Pentium 2 Scaled to 1μm 1μm ZTL
pace matched
1μm ZTL
energy matched
1μm ZTL
linear pace/energy
Common transistors per logic gate 7.5 7.5 1 1 1
Transistor depend 7.5m 7.5m 1m 1m 1m
Provide 2.8V 5V 2.7V 4V 4.2V
Vhi-Vlo at capacitive load. 2.8V 5V 260mV 210mV 180mV
Max clock 300MHz 38MHz (8x
drop via capacitance)
38MHz 380MHz 1GHz – 3GHz
Rise 310ps (est) 2ns (est) 1.82ns 278ps 45ps
Fall 310ps (est) 2ns (est) 2.24ns 242ps 47ps
Propagation 0.95ns (est) 7.5ns (est) 574ps 76.4ps 12.5ps
Energetic energy per transistor 5.73μW 5.73μW TBC TBC TBC
Whole static energy 0.1W 0.1W <0.1W *
Whole lively energy 43W 43W 3.1W 42W 510W
Common gate space Approx 8:1 1 Approx 20:1 Approx 20:1 Approx 2:1
Die space 1/8 1 1/20 1/20 1/2
Layers/danger 24 (est) 24 (est) 8 8 8
Theoretical fab lead time 39 days (est) 39 days (est) 7.5 days 7.5 days 7.5 days
Precise/ manufactured
fab mode
0.35μm 1μm 1μm 1μm 1μm
Equal fab node space saving /infrastructure
time shift
+5 years
0 years
+10 years together with interconnect saving
+10 years together with interconnect saving
+10 years together with interconnect saving
Die space value 1/8 1 1/30 1/30 1/3
Fab time value 1 1 1/5 1/5 1/5
Fab geometry value 8 1 1 1 1
Whole value 1 1 1/150 1/150 1/15

* If 2.5% of the logic was left powered with a 15 fold discount in energy consumption, static energy would drop from 43W to 72mW.
(Editor’s word: if this desk it too large on your browser, copy it and previous it right into a doc)

Price figures within the desk are primarily based on SFN’s Bizen simplified in-fab wafer processing, which may run on customary silicon course of applied sciences utilizing customary CMOS processing gear.

“A 180nm fab utilizing ITM35 delivering ZTL chips with the equal efficiency of 35nm CMOS may have ten instances fewer course of steps than an precise 35nm CMOS course of, leading to a ten fold discount in manufacturing time,” mentioned Summerland. “This interprets right into a 40-50 fold enhance in internet revenue for the Bizen-converted fab.”

On request, he put numbers to this step discount: 500 for 28nm CMOS and 50-80 steps for Bizen.

And the way lengthy Bitzen take?

“The fab infrastructure set up of the ITM is often six months,” Summerland instructed Electronics Weekly. “On the level the foundries have completed their conversion, they might have the power to offer the summary cell primarily based instruments crucial to show current design recordsdata – Verilog, for instance – into ZTL designs.”

What is that this logic?

Bizen-one-transistor-3-input-NORUp-to-date diagrams of SFN transistors and logic have but to be revealed, however SFN did launch an emblem for a 3 enter NOR gate in 2019 (left).

“It’s not precisely right, as ac tunnel currents are concerned and totally different switching traits of the Zpolar transistor,” defined Summerland (see determine under proper).


Bizen ZTL transfer characteristicSwitch attribute:
Enter (blue) strikes from logic 1 (325mV) to logic 0 (375mV), inflicting the output to swing from 0 to 1. The subsequent inverter output (purple) exhibits the excessive transconductance

“To assist clarify, the Zpolar transistor has transconductance which neither a bipolar PNP BJT or unipolar MOS can get near. The ZTL gate’s output is loaded partly by the tunnelling present however largely by an ac tunnelling element. The transconductance and ac-dc tunnelling permit a single transistor logic to behave as a balanced drive, and there’s no shoot-through present.” see present and voltage graphs under.

Bizen current graph“ZTL switching currents proven should not like PMOS or RTL, they’re like CMOS” – Summerland.

The logic gates are fashioned by a single transistor that has inherent tunnelling inside its construction. Each a NAND and NOR gate are fashioned from a single transistor, with totally different tunnelling configurations, Summerland instructed Electronics Weekly.
Bizen voltage graphZTL voltage waveform – with asymetric PWM enter

He went on to elucidate: “ZTL has a excessive impedance enter with a hair set off, paired with a low impedance output [see transfer function above]. The input-output voltage vary is centred across the hair set off which produces a snap output, which grants good noise immunity [see voltage waveform right].”



“The pace enhancement is as a result of phenomenal transconductance of the Zpolar transistor,” defined firm CEO David Summerland. “When mixed with tunnel mechanics, which applies fixed present to transconductance, this provides you big voltage beneficial properties – as much as 1000.”



The place has this come from?

“Bizen has been in improvement at a UK fab for 4 years, and SFN has produced ‘gold customary’ check wafers, which have been charactericed,” mentioned SFN. “The extracted characterisation knowledge has been put right into a JMP knowledge ebook and used to supply SPICE fashions which run within the Cadence design surroundings, and matches the outcomes from the Synopsis wafer course of movement.”

The corporate has additionally described high-voltage Bizen-based units

SFN was based by David Summerland (CEO) and Sam Lodh (COO) in 2016, and relies at The College of Nottingham Innovation Park. It holds 34 patents and at the moment has ~50 personal buyers – buyers “have already been capable of commerce their shares off-market at $100m present valuation”, it claims.
SFN’s web site is operated by its buying and selling arm Wafertrain

Pricey reader: This know-how has prompted a lot head-scratching at Electronics Weekly Towers.
Edifying feedback (under) could be particularly welcome.


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