The D Latch (Quickstart Tutorial)
The D Latch is a logic circuit most often used for storing information in digital programs. It’s based mostly on the S-R latch, but it surely doesn’t have an “undefined” or “invalid” state downside. On this tutorial, you’ll study the way it works, its reality desk, and the best way to construct one with logic gates.
What’s a D Latch?
A D latch can retailer a bit worth, both 1 or 0. When its Allow pin is HIGH, the worth on the D pin might be saved on the Q output. It builds upon the design of the S-R latch, with a number of added logic gates. You’ll be able to see a D Latch circuit based mostly on the S-R latch constructed with NAND gates beneath:
The inverter on the enter makes certain the S and the R inputs are all the time opposites, to keep away from the invalid state of each being 1. The 2 NAND gates create a brand new enter, E (Allow), that permits you to management whenever you wish to change the output to no matter is on the D enter.
Because of this the output Q can solely change when the allow sign is 1. If it’s 0, the output is unaffected by any modifications on D.
It’s also possible to construct a D Latch with AND and NOR gates as follows:
The D Latch will also be used to introduce delay in timing circuits, as a buffer, or for sampling information at particular intervals.
What’s the Distinction Between Latch and Flip Flop?
The phrases latch and flip flop are typically incorrectly used as synonyms since each can retailer a bit (1 or 0) at their outputs.
Whereas a latch can change its output at any time so long as it’s enabled, a flip flop is an edge-triggered machine that wants a clock transition to alter its output.
To construct a D Flip Flop, you’ll want two D latches, like this:
How Does the D Latch Work?
For the reason that output Q solely modifications when the E enter is 1, you’ll get the next reality desk:
| E | D | Q | Description |
|---|---|---|---|
| 0 | X | Q | Reminiscence (no change) |
| 1 | 0 | 0 | Reset Q to 0 |
| 1 | 1 | 1 | Set Q to 1 |
Within the first row of the reality desk, the E enter is 0. Which means the latch will not be enabled, so nothing occurs. The Q output retains no matter worth it had. It doesn’t matter what worth the D enter has, the Q output received’t change, it’s going to preserve its worth as it’s. That is how this circuit “remembers” a bit.
Check out the subsequent two rows. Right here the E enter is 1, so the latch is enabled. Because of this if the D enter is 0, the Q output might be reset to 0. If the D enter is 1, the Q output might be set to 1.
Analyzing the Circuit
You’ll be able to construct a D Latch circuit by including three logic gates to the S-R latch circuit. Within the subsequent picture, you’ll be able to see the D Latch circuit’s bit path when it’s enabled and it has 0 on the D enter.
To investigate the above circuit you might want to keep in mind that the NAND gate solely produces a 0 when its two inputs are each 1. In all different circumstances, it provides a 1.
To start with, the inputs to the first NAND gate are 0 and 1, due to this fact, its output is 1. The 2nd NAND gate has each inputs at 1, so it returns 0.
The outputs of the first and 2nd NAND gates are the inputs to the part of the circuit that represents the essential S-R latch. With that in thoughts, you’ll be able to divide the bits into two teams: People who got here earlier than the S-R latch (Crimson) and people who had been produced by the S-R Latch (Inexperienced).
Lastly, in the event you take a look at the 4th NAND gate. You’ll be able to see that considered one of its inputs is 0 because of the 2nd NAND gate. That info is sufficient to inform you that whatever the worth of its different enter, it’s going to give out 1. This bit is suggestions to one of many inputs of the third NAND gate. The opposite one is 1 because of the 1st NAND gate, so the results of the Q output is 0 – the identical as enter D.
Strive going via this when D is 1 as an alternative, and also you’ll see that the output turns into 1.
From this bit path, you’ll be able to conclude that the D Latch updates the output Q to what’s on the D enter so long as the E enter is 1.
Experiment: Construct Your Personal D Latch Circuit
As a sensible instance, you’ll be able to construct a fundamental D Latch circuit utilizing logic gates and try it out with pushbuttons. R1 and R2 are pull-down resistors to verify the inputs are 0 when the buttons should not pushed:
As you’ll be able to see in part 1 of the picture, Q is 0 (LED L1 off), and each PB1 and PB2 should not pressed.
Subsequent, take a look at part 2 the place PB2 is pushed. You now have a 1 on the D enter, however the output Q stays as 0 as a result of the E enter hasn’t acquired an allow sign but.
Part 3 exhibits how PB1 is pressed, so a 1 on the E enter seems and locations the bit 1 from D to Q. When Q is 1 it activates LED L1.
When PB1 and PB2 return to their authentic states in part 4, LED L1 stays ON indicating that the Q output has not modified.
To vary the output Q you would wish to push PB1 once more.
To assemble the above circuit you want:
- 4 NAND gates (Ex CD4011)
- One NOT gate (Ex CD4049 or CD4069)
- 2x pushbuttons
- 1x LED
- 2x 10 kΩ resistors (R1 and R2)
- 1x 330 Ω resistors (R3)
Questions?
Do you will have any questions concerning the D Latch and the way it works? Let me know within the feedback beneath.
